1. Field of the Invention
The invention relates to data communication, and more particularly, to an apparatus for serial data communication among a plurality of integrated circuit (xe2x80x9cICxe2x80x9d) chips which allows a reduced number of signal lines to be interconnected among the IC chips.
2. Description of the Related Art
In a chip set that includes several IC chips, a number of signal lines are often interconnected among the IC chips for data transmission among the same. The provision of a large number of signal lines in a chip set has several drawbacks. First, the size of the package increases in proportion to the number of signal lines. Second, the complexity of assembly of the chip set increases as the number of signal lines increases. Third, manufacturing cost is increased due to an increase in the chip area required to accommodate the large number of signal lines.
It is a customary practice to arrange the signal lines in parallel between two separate IC chips in order to attain a high data transmission rate. However, in order to minimumize the number of signal lines among a large number of IC chips, there are two conventional methods that can be used. The first method includes the use of multiplexers with time-share sampling, and the second method includes the use of serial transmission techniques. Examples of systems using these two methods are illustrated in FIG. 1 and FIG. 2.
FIG. 1 illustrates an exemplary system using the method of multiplexing with time-share sampling, on a chip set that includes a first IC chip 10 and a second IC chip 11. The first IC chip 10 includes a control unit 13, a demultiplexer 14, and four identical, independent data receiving units 120, 121, 122, 123. The second IC chip 11 includes a multiplexer 16 and four identical data transmitting units 150, 151, 152, 153 associated respectively with the data receiving units 120, 121, 122, 123 in the first IC chip 10.
In the first IC chip 10, the data receiving units 120, 121, 122, 123 are wire connected to the demultiplexer 14 by the buses 17a, 17b, 17c, and 17d, respectively. In the second IC chip 11, the data transmitting units 150, 151, 152, 153 are wire connected to the multiplexer 16 by means of the buses 17f, 17g, 17h, and 17i, respectively. The demultiplexer 14 is wire connected to the multiplexer 16 by the bus 17e. Moreover. the demultiplexer 14 in the first IC chip 10 is wire connected to the control unit 13, which is also in the first IC chip 10, by the internal bus 18, while the multiplexer 16 in the second IC chip 11 is wire connected to the control unit 13 by the external bus 19. Since there are four source devices (i.e., the data transmitting units 150, 151, 152, 153) that are to be multiplexed by the multiplexer 16 for data transmission, and since there are four destination devices (i.e., the data receiving units 120, 121, 122, 123) that are to be selected by the demultiplexer 14 for reception of data from the source devices, therefore, the buses 18, 19 each consist of two signal lines from the control unit 13, serving to transmit a set of two control bits respectively to the multiplexer 16 and to the demultiplexer 14 for selecting a respective one of the four source devices. When a certain pair of data transmitting units and data receiving units is selected to use the common bus 17e for data transmission, for example, the second data transmitting unit 151 and the associated data receiving unit 121, the control unit 13 generates two control bits which are sent respectively over the bus 18 and the bus 19 to the demultiplexer 14 and the multiplexer 16. In response, in the first IC chip 10 the demultiplexer 14 connects the bus 17b to the receive end of the common bus 17e and, in the second IC chip 11 the multiplexer 16 connects the bus 17g to the transmit end of the common bus 17e. 
There are, however, two drawbacks to the system configuration of FIG. 1. First, the clock rate of the control bits from the control unit 13 should be much faster than the data transmission rate in order to allow fast switching between the four multiplexed devices. Second, power consumption in the chip set is very high.
FIG. 2 illustrates an exemplary system using a serial transmission method on a chip set that includes a first IC chip 20 and a second IC chip 21. A set of at least four signal lines 22, 23, 24, 25 is used for data transmission between the first IC chip 20 and the second IC chip 21. The signal line 22 allows the first IC chip 20 to transmit a Chip Select signal to the second IC chip 21; the signal line 23 allows the first IC chip 20 to transmit a Serial Clock signal to the second IC chip 21. The signal line 24 allows the second IC chip 21 to transmit serial binary data to the first IC chip 20; the signal line 25 allows the first IC chip 20 to transmit serial binary data to the second IC chip 21.
There are, however., two drawbacks to the system configuration of FIG. 2. First, the number of signal lines between the two IC chips 20, 21 is not minimumized since the data transmission between the two IC chips 20, 21 is carried out over two separate lines (i.e., the signal lines 24, 25) rather than one. Second, data communication between the two IC chips 20, 21 is under the control of a module in the first IC chip 20, and the second IC chip 21 is unable to issue any requests for data transmission. Therefore, the system configuration of FIG. 2 is not suitable for data communication among a large number of IC chips.
It is therefore an object of the invention to provide an apparatus for serial data communication using a reduced number of signal lines among a plurality of IC chips.
In accordance with the foregoing and other objects of the invention, a new and improved apparatus for serial data communication among a plurality of IC chips is provided. In the apparatus, one IC chip acts as a master, while the other chip(s) are slaved to the master. In response to conditions internal to the master chip, or in response to a request from at least one slave chip, the master chip generates a transfer control signal and a synchronization clock signal. The transfer control signal defines a transfer phase during which data transfer among the chips can take place. The chips take turns sending and receiving data in a multiplexed fashion, with sending and receiving parties designated by a count of synchronization clock signal cycles. The synchronization clock signal is generated at a high frequency, to allow fast data transfer. The data communication between the IC chips requires only a reduced number of signal lines, which allows the number of pins required for connection of the two IC chips, as well as manufacturing costs, to be significantly reduced.
Thus, the apparatus according to the invention includes means for generating a transfer request signal and means for generating a transfer control signal and a synchronization clock signal in response to the transfer request signal, wherein the synchronization clock signal has a plurality of cycle periods. The apparatus also includes means for counting the cycle periods of the synchronization clock signal to produce a cycle count. A data transmitting means is provided for transmitting data in response to the transfer control signal under control of the cycle count. A data receiving means receives the data transmitted by the data transmitting means in response to the transfer control signal also under the control of the cycle count.
According to a further aspect of the invention, the means for generating a transfer request signal includes a first transfer request signal generating means located on the first IC chip and a second transfer request signal generating means located on the second IC chip. The means for generating a transfer control signal and a synchronization clock signal is located on the first IC chip. The means for counting the cycle periods of the synchronization clock signal includes a first cycle period counting means located on the first IC chip and a second cycle period counting means located on the second IC chip. The data transmitting means includes a first data transmitting means located on the first IC chip and a second data transmitting means located on the second IC chip. The data receiving means includes a first data receiving means located on the first IC chip and a second data receiving means located on the second IC chip.
According to another aspect of the invention, the apparatus also includes means, responsive to the cycle count, for selecting between the first data transmitting means and the second data transmitting means and for enabling only the selected data transmitting means to transmit data, and further includes means, responsive to the cycle count, for selecting between the first data receiving means and the second data receiving means and for enabling only the selected data receiving means to receive data.
According to another particular embodiment of the invention, the first transfer request signal generating means and the first data transmitting means are included in a master output encoder, and the second transfer request signal generating means and the second data transmitting means is included in a slave output encoder. The means for generating a transfer control signal and a synchronization clock signal is included in a master control unit. The first data receiving means is included in a master input decoder. The second data receiving means is included in a slave input decoder. The master control unit further includes means for generating a master output control signal to control the master output encoder, and means for generating a master input control signal to control the master input decoder. The second IC chip further includes a slave control unit. The slave control unit includes means for generating a slave output control signal to control the slave output encoder, and means for generating a slave input control signal to control the slave input decoder.
According to still another particular embodiment of the invention, the apparatus comprises a transfer signal control line for transferring the transfer control signal from the master control unit to the slave control unit; a synchronization clock signal line for transferring the synchronization clock signal from master control unit to the slave control unit; and a data line for passing data from the master output encoder to the slave input decoder, and from the slave output encoder to the master input decoder.
A method according to the invention, by which the apparatus of the invention may be used, includes the steps of generating a transfer request signal; generating a transfer control signal and a synchronization clock signal in response to the transfer request signal, wherein the synchronization clock signal has a plurality of cycle periods; counting the plurality of cycle periods of the synchronization clock signal to produce a cycle count; transmitting data in response to the transfer control signal under control of the cycle count, and receiving the data transmitted by the data transmitting means in response to the transfer control signal under control of the cycle count.
According to a further aspect of the invention, the method also may include the steps of selecting, in response to the cycle count, between a first data transmitting means and a second data transmitting means and for enabling only the selected data transmitting means to transmit data; and selecting, in response to the cycle count, between a first data receiving means and a second data receiving means and for enabling only the selected data receiving means to receive.
The data communication between the IC chips requires only a reduced number of signal lines, which allows the number of pins required for connection of the two IC chips, as well as manufacturing costs, to be significantly reduced.